1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to the regulation of power in integrated circuits using pulse width modulation (PWM) techniques.
2. Background of the Invention
Pulse width modulation techniques are an essential part of the control of many of the power related systems found in both commercial and industrial equipment. The main application areas include digital motor control, digital switch mode power supply control, uninterruptible (UPS) power supplies, and other forms of power conversion.
Although duty cycle control adjustment is one of the most commonly used PWM control methods, phase adjustment between a plurality of PWM channels is important in many power supply applications. The PWM phase relationship is important in two power supply categories, multi-phase power applications and resonant switch full bridge applications.
In the multi-phase power applications, a constant phase relationship is established between PWM channels prior to operation of the power stage. Power delivery is then controlled by duty cycle adjustment. The ability to be able to dynamically reconfigure a number of phases (depending on load and other parameters) becomes increasingly important. The phase relationship must be re-configured on-the-fly depending on system conditions.
With respect to the resonant switched full bridge applications the duty cycle remains essentially constant, while the power delivery is controlled entirely by the phase relationship between PWM channels. The phase adjustment occurs at very high up-date rates which in many cases can equal the PWM switching frequency.
Referring to FIG. 1, a PWM generator according to the prior art is shown. Period register 11 applies an output signal to a first input terminal of comparator 14, while counter 12 applies output signals to a second input terminal of comparator 14 and to a first input terminal of comparator 15. The compare register 13 applies output signals to a second input terminal of comparator 15. The output signal of comparator 14 is applied to the clear terminal of Q flip-flop 16 and to the reset terminal of counter 12, while the output terminal of comparator 15 is applied to the set terminal of Q flip-flop 16. The system clock signal is applied to the clock terminal of counter 12. The Q terminal of Q flip-flop 16 provides the PWM signal, i.e., the signal controlling the activation of the power components.
The operation of FIG. 1 can be understood by reference to FIG. 2, the waveforms for circuit shown in FIG. 1. The counter 12 (providing the system time base) is activated by the system clock, typically at 20–100 MHz, and counts upward. The count value is transmitted over a 16 bit bus (CTR[0–15]) to the comparators. Comparator 14 provides a comparison to period register and determines the PWM period, i.e., the frequency of the operation. The output signal of comparator 14 reset the counter when the COUNTER VALUE equals the PERIOD VALUE. Comparator 15 provides a comparison of the counter 12 value with the compare register 13. The output signal of comparator 15 sets the duty cycle when COUNTER VALUE equals COMPARE REGISTER VALUE. These two events drive CLEAR/SET logic to generate the PWM waveform shown in FIG. 2. The ramp waveform is a virtual one and only represents the upward counting vales of counter 12 over time. The Y-axis represents the counter 12 value while the x-axis represents time.
A need has therefore been felt for apparatus and an associated method having the feature that the phase adjustment in a PWM system is accomplished under software control. It would be yet another feature of the apparatus and associated method to provide a phase control register, the phase value (lag or lead) being written to the phase control register. It would be a still further feature of the present invention to incur relatively little software overhead when performing the phase adjustment. It would be a still further feature of the apparatus and associated method to update the phase at the end of each PWM cycle, thereby avoiding transitory glitches. It would be yet another feature of the apparatus and associated method to provide non-software dependent, reliable synchronizing mechanism that “re-locks” PWM channels to the programmed phase control register value every PWM cycle. It would be yet a further feature of the apparatus and associated method to support a friendly programmer interface/model with a microprocessor or DSP. It would be still further feature of the apparatus and associated method to support both up-count (asymmetrical) PWM applications and up/down count (symmetrical) PWM applications.